Without limiting the scope of the invention, its background is described in connection with methods for forming a stacked, six transistor static memory cell using MOSFET technology or stacked 6T SRAM as an example.
Under current MOSFET transistor technology, problems associated with short channel effects, source/drain (moat) junction capacitance, reliability and packing density arise as MOSFET technology is scaled to smaller dimensions.
MOSFET short channel effects increase as the source/drain junction depth increases. Thus, it is desirable to minimize the depth of such junctions, especially as the length of the transistor decreases. One approach to minimizing source/drain junction depth, with respect to the gate oxide/silicon substrate interface, is to form raised source/drain regions.
MOSFET source/drain junction capacitance increases as source/drain junction area increases. Thus, it is desirable to minimize the moat area, which will also improve the packing density of integrated circuits. One approach is to form contacts from metal-1 to the source/drain regions over field oxide, rather than directly over the moat regions.
Under standard MOS transistor design, the source/drain area must considerably exceed the contact to metal-1 size to prevent junction leakage into the underlying substrate. This is a result of potential etching error due to misalignment of the contact to metal-1 over the source/drain area. If the contact overlies the source/drain, the contact etch may penetrate the PN junction edge of the source/drain, thereby short-circuiting that junction. However, if the contact can overlie field oxide, there is no need for the larger source/drain area. Thus, the source/drain area may be reduced with a corresponding reduction in size of the transistor. Reduced transistor size gives rise to higher packing density.
Previously developed attempts to form a conducting layer from moat over field oxide in addition to the formation of raised moat regions have created attendant problems. Quite often, the processes involved are complicated and require extreme process control.
One such prior attempt comprises the non-reactive UPMOS process. This process deposits source/drain polysilicon over a patterned gate structure followed by resist planarization and etch-back. The etch removes the polysilicon over the gate, while not removing the polysilicon over the moat and field oxide regions. This process has the disadvantages of utilizing a resist-etch-back (REB) process to define the final thickness of the polysilicon over the moat regions. In particular, the REB process does not utilize an etch-stop layer and thus can lead to difficulty in control and uniformity of the final polysilicon thickness over moat. It should be noted that the final polysilicon thickness ultimately determines the source/drain junction depth of the resulting MOSFET device.
A second prior art solution is the reactive UPMOS process. In this process, a dopant diffusion source over a patterned gate is used to dope the polysilicon deposited over the patterned gate, followed by a selective etch process. In this process, the doped polysilicon (over the gate) is etched faster than the undoped polysilicon which lies over the moat and field oxide regions. This process has several disadvantages. First, the use of a diffusion process to dope the overlying polysilicon is unreliable. The diffusion process is not precisely controllable due to both interfacial oxide effects between the dopant source and the overlying polysilicon and also due to the adverse characterized diffusion of dopants in polysilicon. Second, a selective etch with no etch-stop mask can cause difficulties in the control and uniformity of precise polysilicon thickness over moat. Third, a high gate-to-source/drain capacitance can result if insufficient dopant diffusion reaction causes the remaining polysilicon thickness over moat to be equivalent to the thickness of the gate stack.
A third prior art solution has comprised a TiN process which forms a TiN layer extending from the moat over the field oxide regions. This process, even if used in conjunction with selective epitaxy to form raised moat regions, requires a large moat width (and thus area) since the TiN layer must overlap the moat by approximately 0.8 .mu.m to satisfy minimum contact resistance requirements. Due to large moat width, there is a consequent requirement of larger device size. Further, the larger moat area required by the TiN process thus results in an increased source/drain junction capacitance.
In addition to forming the aforementioned standard MOSFET (typically the N-channel MOSFET), in the example of a stacked 6T SRAM it is necessary to connect the gate of the aforementioned MOSFET to the semiconductor film of a thin film transistor (TFT) MOSFET (typically a P-channel MOSFET). The process used to make this connection in prior art stacked 6T SRAMs is generally independent of the process used to form the standard MOSFET. Hence, the prior art connection method described below may be regarded as applying to any of the aforementioned prior art MOSFET methods.
The prior art process steps which follow one of the aforementioned methods for forming the standard MOSFET transistor consist of depositing an interlevel oxide (ILO) to provide isolation between conductive elements, opening contact holes in ILO, depositing TFT gate material on top of ILO and above appropriate contact hole etched in the ILO to form a connection between the lower level conductors and the TFT gate material, patterning the TFT gate material to form a gate for a first TFT, depositing TFT gate oxide, patterning/etching a hole in TFT gate oxide above TFT gate material, depositing TFT semiconductor film for a second TFT on top of gate oxide and above appropriate contact hole etched in the gate oxide to form a connection between the gate of the first TFT and the semiconductor film of the second TFT. Several disadvantages exist with this prior art method. One disadvantage is that this method requires patterning of resist on top of the TFT gate oxide layer, thus leading to the possibility of chemical contamination of the TFT gate oxide arising from contact between the gate oxide and the resist prior to deposition of the TFT semiconductor film. Such chemical contamination can lead to defects and associated breakdown of the oxide when a voltage is applied across the oxide. Another disadvantage is the possibility of interfacial oxide on the TFT gate forming in the area of the contact hole--hindering the connection between the TFT gate and the TFT channel film. Using the prior art technique, a hydrogen fluoride (HF) deglaze to remove this interfacial oxide prior to TFT channel film deposition, can lead to non-uniform wet etching of the TFT gate oxide, especially in areas where the TFT gate oxide overlies corners of underlying topography for which the oxide might be thinner or under stress. Still another disadvantage is the necessity to deposit the TFT channel film overlapping the contact hole in the gate oxide to compensate for layer to layer mask misalignment.
Therefore, a need has arisen for a simple and more reliable process to create a 6T stacked SRAM structure having transistors with raised source/drain regions and with a conducting layer extending from moat regions over field oxide regions. A need further exists for a more reliable method to connect different layers of semiconductor and/or conductor materials with interposing insulator layers. More specifically, a need exists for a method to connect the TFT gate for a first TFT in this 6T stacked SRAM to the TFT semiconductor film for a second TFT.